32207 ms pc 20060719-s00002 no.a0692-1/8 any and all sanyo semiconductor products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. consult with your sanyo semiconductor representative nearest you before using any sanyo semiconductor products described or contained herein in such applications. sanyo semiconductor assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all sanyo semiconductor products described or contained herein. lv5609lp overview the lv5609lp is vertical clock driver for ccd. functions ? ternary output 2ch ? binary output 2ch ? sht output 1ch ? output on resistance : 30 typ specifications absolute maximum ratings at ta = 25 c, v ss = vm = 0v parameter symbol conditions ratings unit v dd max 6v vh max 20 v vl max -10 v maximum supply voltage vh-vl max 24 v allowable power dissipation pd max with specified substrate * 0.8 w operating temperature topr -20 to +80 c storage temperature tstg -40 to +125 c * : specified substrate : 40 50 0.8mm 3 , glass epoxy four-layer (2s2p) board allowable operating ratings at ta = 25 c, v ss = vm = 0v ratings parameter symbol conditions min typ max unit v dd 2.0 3.3 5.5 v vh 15 17 v vl -8.5 -7.5 -4 v supply voltage vh-vl 23.5 v cmos input high voltage v in h 0.8v dd v dd v cmos input low voltage v in l -0.1 0.4 v bi-cmos lsi for ccd vertical clock driver orderin g numbe r : ena0692
lv5609lp no.a0692-2/8 electrical characteristics at ta = 25c, v dd = 3.3v, v ss = 0v, vh = 15v, vl = -7.5v, vm = 0v, unless otherwise specified ratings parameter symbol conditions min typ max unit i dd v dd pin 1 a ih vh pin 10 a static current drain il vl pin 1 a i dd v dd pin see *1 and *2. 1 ma ih vh pin see *1 and *2. 2.4 4.5 ma dynamic current drain il vl pin see *1 and *2. 3 5 ma rl i o = +10ma 20 30 rm i o = 10ma 30 45 rh i o = -10ma 30 40 output on resistance rsht i o = -10ma 30 40 tplm no load 200 ns tpmh no load 200 ns tplh no load 200 ns tpml no load 200 ns tphm no load 200 ns propagation delay time tphl no load 200 ns vl vm v1, v3 see *1. 800 ns ttlm vl vm v2, v4 see *1. 800 ns ttmh vm vl v1, v3 see *1. 800 ns rise time ttlh vl vh sht see *1. 200 ns vm vl v1, v3 see *1. 800 ns ttml vm vl v2, v4 see *1. 800 ns tthm vh vm v1, v3 see *1. 800 ns fall time tthl vh vl sht see *1. 200 ns *1 : refer to the ccd equivalent load shown below. *2 : refer to the timing waveform on page 7. v1 (ternary) v2 (binary) v4 (ternary) v3 (binary) sht 2000pf 2000pf 1000pf 3000pf 3000pf 1000pf 2000pf 2000pf 1600pf
lv5609lp no.a0692-3/8 package dimensions unit : mm (typ) 3322 side view side view bottom view top view 3.5 0.25 0.83 3.5 0.4 (0.035) 0.5 (0.5) (0.125) (c0.116) (0.13) 1 6 24 19 18 13 12 7 sanyo : vct24(3.5x3.5)x01 0 0.8 0.36 0.07 0.4 0.2 0.15 0.6 1.0 ? 20 80 60 20 40 010 0 ambient temperature, ta ? c allowable power dissipation, pd max ? w pd max ? ta independent ic specified circuit board : 40 50 0.8mm 3 , glass epoxy four-layer (2s2p) board with specified substrate
lv5609lp no.a0692-4/8 pin assignment pin function pin no. name mode 1 vl lo power for output (-7.5v system) 2 sht level shift output (binary vh, vl) 3 v4 level shift output (binary vm, vl) 4 v3 level shift output (ternary vh, vm, vl) 5 v2 level shift output (binary vm, vl) 6 v1 level shift output (ternary vh, vm, vl) 7 vm gnd for output 8 nc 9 vh hi power supply for output (15v system) 10 nc 11 nc 12 xv1 v1 transfer pulse input 13 xsg1 v1 read pulse input 14 xv2 v2 transfer pulse input 15 xv3 v3 transfer pulse input 16 xsg3 v3 read pulse input 17 xv4 v4 transfer pulse input 18 xsht sht pulse input 19 nc 20 v dd power supply for input buffer (3.3v system) 21 v ss gnd for input buffer 22 nc 23 nc 24 nc 1 2 3 4 5 6 7 8 9 10 11 12 18 17 16 15 14 13 24 23 22 21 20 19 vl sht v4 v3 v2 v1 vm nc vh nc nc xv1 xsg1 xv2 xv3 xsg3 xv4 xsht nc v dd v ss nc nc nc top view
lv5609lp no.a0692-5/8 block diagram logical function table input output xv1 xv3 xsg1 xsg3 xv2 xv4 xsht v1 v3 v2 v4 sht l l x x vh x x l h x x vm x x h l x x vl x x h h x x vl x x x x l x x vm x x x h x x vl x x x x l x x vh x x x h x x vl 9 6 5 7 4 3 2 1 20 12 13 14 15 16 17 18 21 30 30 30 30 input buffer v dd xv1 xsg1 xv2 xv3 xsg3 xv4 xsht v ss vh v1 v2 vm v3 v4 sht vl 0.1 f 1 f 1 f level shift & output buffer 30
lv5609lp no.a0692-6/8 timing chart xsg1 xsg3 xv1 to xv4 v dd v ss v dd v ss 50% 50% 50% tpmh ttlm vh 90% ttml v1 v3 10% 90% tplm vm vl 10% tpml 10% 90% tplm vm vl tpml ttlm v2 v4 ttml xsht v dd v ss 50% 50% 10% 90% tplh vh vl tphl ttlh sht tthl ttmh tphm tthm
lv5609lp no.a0692-7/8 63.5 s 2 s 127 s 2.5 s 16.7ms 2.5 s 63.5 s 2 s xv3 xv1 xv2 xv4 xsg1 xsg3 xsht xv1 xv2 xv3 xv4 0 s0.7 s1.4 s2.1 s2.8 s3.5 s4.2 s4.9 s ccd equivalent load measurement timing waveform enlarged view of overlapped portion
lv5609lp ps no.a0692-8/8 specifications of any and all sanyo semiconductor products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. sanyo semiconductor co., ltd. strives to supply high-quality high-reliability products. however, any and all semiconductor products fail with some probability. it is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. when designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. in the event that any or all sanyo semiconductor products (including technical data,services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of sanyo semiconductor co., ltd. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equipment, refer to the "delivery specification" for the sanyo semiconductor product that you intend to use. information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. sanyo semiconductor believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. this catalog provides information as of march, 2007. specifications and information herein are subject to change without notice.
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